1. Field of the Invention
The present invention relates to a drive control circuit of a charged pump circuit for raising a voltage inside an LSI in a semiconductor integrated circuit, and more particularly to a drive control circuit of a charged pump circuit for inhibiting an increase in consumed current caused by an excess of ability of the charged pump at the time of an increase in the voltage of an operating power source of the LSI and, at the same time for compensating for a reduction in the ability of the output of the increased voltage of the charged pump at the time of a reduction in the operating power source.
2. Description of the Related Art
No related art has been found which describes a technique with respect to a charged pump circuit which increases the voltage inside an LSI in a semiconductor integrated circuit, or a technique for preventing an increase in the consumed current caused by an excess of ability of the charged pump at the time of an increase in the operating power source voltage and compensating for a reduction of output ability in the increased voltage of the charged pump at the time of a reduction in the operation power source voltage.
FIG. 12 shows a structure of a general charged pump circuit. In FIG. 12, NMOS diodes ND1 through NDn (n is an integer) and NDout are connected in series between an input terminal 100 and an output terminal 200. To each of the nodes N1 through Nn of the NMOS diodes ND1 through NDn, one end of n capacitors C1 through Cn is connected respectively. To the other end of the capacitor C(2(m-1)+1) (m&lt;n and m is an integer not less than 1) out of n capacitors C1 through Cn, a clock .phi.1 is supplied via inverters INV1, INV3, . . . INV(n-1).
Furthermore, a clock .phi.2 is supplied to the other end of the capacitor C(2m) via inverters INV2, INV4, . . . , INVn.
Furthermore, a power source voltage VDD is applied to the input terminal 100. As shown in FIG. 13B, clocks .phi.1 and .phi.2 are clock signals which change in levels in a compensating manner at a timing at which high level periods do not overlap each other. The amplitude thereof is the VDD. The operation of the charged pump circuit shown in FIG. 12 will be briefly explained. When the threshold voltage of NMOS diodes ND1 through NDn and ND out is set to VD, the potential of node 1 is set to VDD-VD when the clock .phi.1 is on a low level. When the clock .phi.1 is on a high level and the clock .phi.2 is on a low level, current flows from the node N1 to the node N2, from the node N3 to the node N4, . . . , and from the node N(n-1) to the node Nn, and the potential of the node N(2m) becomes higher than the potential of the node N(2m+1) by the threshold voltage VD of the NMOS diode (for reference, m is either 0 or an integer not less than 1).
Next, when the clock .phi.1 falls to a low level, the potentials of the nodes N1, N2, . . . , N2m, . . . , Nn tend to fall by the amount of the VDD because of the coupling of capacitors. However, current is supplied from the left side, and the potentials are raised to a higher level than when the clock .phi.1 was previously on a low level. Next, when the clock .phi.2 is raised to a high level, a current is supplied from the node N(2m-1) to the node N(2m). When the clock .phi.2 is brought back to the low level, a current is supplied from the node N(2m-2) to the node N(2m-1) so that the potential of the node N(2m-1) is raised to a higher level than the potential thereof at the time of the previous cycle.
When the capacity of the capacitors C1 through Cn is denoted by C, the frequency of the clocks .phi.1 and .phi.2 is denoted by f, the output amplitude voltage of the inverters INV1 through INVn is denoted by VDD, and the output average current value at an output terminal 200 of the charged pump circuit is denoted by Iout, the potential of each node is raised by the amount (VDD-VD-Iout/(C.multidot.f)) as shown in FIG. 13A as compared with the potential of the node by the adjacent input terminal 100. Here, Iout/(C.multidot.f) denotes a charging and discharging voltage in the capacitors C1 through Cn. In other words, since the output voltage Vout at an output terminal of the charged pump circuit shown in FIG. 12 is raised by the amount (VDD-VD-Iout/(C.multidot.f)) for each one step of the NMOS diode, the following mathematical formula is established. EQU Vout=VDD+n.multidot.(VDD.sup.- VD-Iout/(C.multidot.f))-VD (1)
The average consumed current IDD of this charged pump circuit excluding a through current of the inverters (consumed current at the time of ON and OFF inside the inverters) is the sum total of the current values at which each of the inverters INV1 through INVn charges and discharges the capacitors C1 through Cn at the output average current value lout, and the following mathematical formula is established. EQU IDD=n.multidot.Iout (2)
In order to set the output voltage Vout at the output terminal 200 to a constant level, the output average current value Iout 1 of the charged pump circuit becomes equal to the sum total of the output average current value Iout and a Zener current Iz in the case where Zener diodes ZD 1 and ZD 2 are connected between the output terminal 200 and an earth as shown in FIG. 14. If the output voltage of the charged pump circuit shown in FIG. 14 which circuit is clamped at the Zener diodes ZD 1 and ZD 2 is denoted by Vz, the following mathematical formula is established.
Vz=VDD+n.multidot.(VDD-VD-(Iout+Iz)/(C.multidot.f))-VD=Vout-n.multidot.Iz/ (C.multidot.f) (3)
From the mathematical formulae (1), (2) and (3), the Zener current Iz, and the average consumed current IDD is established in the following manner. EQU Iz=(Vout-Vz)/n.multidot.C.multidot.f (4) EQU IDD=n.multidot.(Iout+Iz) (5)
When the output average current value Iout is at a constant level, the output voltage Vout increases as seen from the mathematical formula (1) at the time when the power source voltage VDD increases, and the Zener current Iz and the average consumed current IDD increase according to the mathematical expressions (4) and (5). FIGS. 15A and 15B show operating waveforms of a charged pump circuit having the structure shown in FIG. 14.
In a conventional charged pump circuit, since the number of steps of the NMOS diodes, namely the number of steps n of the charged pump circuit and the capacity C of the capacitors (1-Cn) which are connected to each of the nodes of the NMOS diodes, are fixed values which are determined at the time of the circuit design, there arises a problem that an unutilized Zener current Iz which flows to the Zener diodes for use in the output voltage clamp increases and the average consumed current IDD of the inverters increases with an increase of the power source voltage VDD in the case where the output average current value Iout of the charged pump circuit is constant.